A read-only memory device is fabricated on a semiconductor substrate in association with another semiconductor device, such as a data processing unit and an I/O unit, or separately from these units for storing coded instructions or fixed data. For semiconductor manufacturers, it is still an important object to minimize the occupation area of the read-only memory device, and attempts have therefore been made to save the occupation area for the complete read-only memory device.
One of the attempts is disclosed by John A. Bayliss et al in "The Interface Processor for the 32b Computer", the digest of technical papers of 1981 IEEE International Solid-State Circuits Conference, pages 116 to 117. The interface processor proposed by John A. Bayliss et al has the read-only memory array consisting of a plurality of memory cells each having a two-bits per cell structure. The memory cell structure comprises two n-type impurity regions formed in a surface portion of a p-type semiconductor substrate covered with an insulating layer and a gate electrode formed on the insulating film and located over a channel forming region between the two n-type impurity regions. The channel forming region has a preselected width depending upon a combination of two bits of information stored therein.
Namely, when a memory cell stores two logic "0" bits, the two n-type impurity regions 1 and 2 are spaced apart from the channel forming region 3 located under the gate electrode 4 as will be seen from FIG. 1 (A), then no current flows between the n-type impurity regions 1 and 2 even if a certain positive voltage level is applied to the gate electrode 4. When a memory cell stores an information consisting of the logic "0" bit and the logic "1" bit, the n-type impurity regions 5 and 6 are connected to the channel forming region 7 through n-type lug portions 8 and 9 which are merged into the channel forming region 7, respectively, as shown in FIG. 1 (B), then a small amount of current flows between the n-type impurity regions 5 and 6 through the lug portions 8 and 9 and the channel induced in the channel forming region 7 by the agency of the certain positive voltage level applied to the gate electrode 10. In FIG. 1 (C) is illustrated another memory cell configuration storing an information consisting of the logic "1" bit and the logic "0" bit. The memory cell illustrated in FIG. 1 (C) has lug portions 11 and 12 wider than the lug portions 8 and 9. As the amount of current is in proportion to the width of the lug portions, a substantial amount of current flows between the n-type impurity regions 13 and 14 through the lug portions 11 and 12 and the channel induced in the channel forming regions 15 by the agency of the certain positive voltage level applied to the gate electrode 16. However, if a memory cell is arranged to store two logic "1" bits of information, the memory cell is provided with lug portions 17 and 18 wider than the lug portions 11 and 12 as shown in FIG. 1 (D). Then, a current greater than the current flowing through the memory cell illustrated in FIG. 1 (C) flows between the n-type impurity regions 19 and 20 when the certain positive voltage level is applied to the gate electrode 21. Thus, the memory cells proposed by John A. Bayliss et al allow currents different in amount from one another to flow therethrough depending upon the bits of information stored therein, so that the stored information can be readable by measuring the voltage level at the impurity region.
The memory cell structure proposed by John A. Bayliss et al has achieved substantial reduction in total occupation area; however, problems have been encountered in the memory cell structure proposed by John A. Bayliss et al in complexity in circuit configuration for detecting a small amount of difference in voltage level between the memory cells storing the different informations, respectively. This complexity results in unstable circuit behavior and limitation to high-speed performance.
It is therefore an important object of the present invention to provide a semiconductor memory device having a memory cell structure capable of storing two bits of information which are read out based on the existence or nonexistence of the current.
It is another important object of the invention to provide a semiconductor memory device having a memory cell structure from which a stored information is read out at an improved speed.